View M48Z512A-70PM1NBSP_311444.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M48Z512A M48Z512AY, M48Z512AV
4 Mbit (512 Kbit x 8) ZEROPOWER(R) SRAM
FEATURES SUMMARY s INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY
s
Figure 1. 32-pin PMDIP Module
CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION TWO WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) - M48Z512A: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V - M48Z512AY: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V - M48Z512AV: VCC = 3.0 to 3.6V 2.8V VPFD 3.0V BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 512K x 8 SRAMs SURFACE MOUNT CHIP SET PACKAGING (Figure 2) INCLUDES A 28-PIN SOIC and A 32LEAD TSOP (SNAPHAT(R) Top to be ordered separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY SNAPHAT HOUSING (BATTERY) IS REPLACEABLE
32
32 1
s
s
s
PMDIP32 (PM) Module
Figure 2. Surface Mount Chipset Solution
SNAPHAT (SH) Crystal / Battery
s
s
s
s
SOH28 (MH)
s
1
TSOP II 32 (NC) (10 x 20mm)
January 2002
1/22
M48Z512A, M48Z512AY, M48Z512AV
TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 DIP Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Hardware Hookup for SMT Chipset (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chipset Solution (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC Measurement Load Circuit (Figure 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating Modes (Table 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable or Output Enable Controlled, READ Mode AC Waveforms (Figure 8.). . . . . . . . . . . . . 9 Address Controlled, READ Mode AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Enable Controlled, WRITE AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable Controlled, WRITE AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Mode AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Down/Up Mode AC Waveforms (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Down/Up AC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Down/Up Trip Points DC Characteristics (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Supply Decoupling and Undershoot Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SNAPHAT Battery Table (Table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22
M48Z512A, M48Z512AY, M48Z512AV
DESCRIPTION The M48Z512A/Y/V ZEROPOWER(R) RAM is a non-volatile, 4,194,304-bit Static RAM organized as 524,288 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP Module. For surface mount environments ST provides a Chip Set solution consisting of a 28-pin, 330mil SOIC NVRAM SUPERVISOR (M40Z300/W) and a 32-pin TSOP Type II (10 x 20mm) LPSRAM (M68Z512/W) packages. Both 5V and 3V versions are available (see Table 2, page 5). The unique design allows the SNAPHAT (R) battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is "M4Z32-BR00SH1."
Figure 3. Logic Diagram
VCC
Table 1. Signal Names
A0-A18 DQ0-DQ7 Address Inputs Data Inputs / Outputs Chip Enable Input Output Enable Input WRITE Enable Input Supply Voltage Ground
19 A0-A18 M48Z512A M48Z512AY M48Z512AV
8 DQ0-DQ7
E G W VCC VSS
W E G
VSS
AI02043
3/22
M48Z512A, M48Z512AY, M48Z512AV
Figure 4. DIP Connections
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48Z512A 8 M48Z512AY 9 M48Z512AV 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI02044
Figure 5. Block Diagram
VCC
A0-A18
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
512K x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERY
VSS
AI02045
4/22
M48Z512A, M48Z512AY, M48Z512AV
Figure 6. Hardware Hookup for SMT Chipset
THS(2,3) VOUT SNAPHAT BATTERY(4)
VCC E2
M40Z300/W E E1CON E2CON E3CON E4CON A RST B BL VSS W E
M68Z512/W DQ0-DQ7
A0-A18
VSS
AI03631
Note: For pin connections, see individual data sheets for M48Z300/300W and M68Z512/512W at www.st.com. 1. Connect THS pin to VOUT if 4.2V VPFD 4.5V (M48Z512AY) or connect THS pin to VSS if 4.5V VPFD 4.75V (M48Z512A). 2. Connect THS pin to VSS if 2.8V VPFD 3.0V (M48Z512AV). 3. SNAPHAT (R) Top ordered separately.
Table 2. Chipset Solution
NVRAM M48Z512A M48Z512AY M48Z512AV LPSRAM M68Z512 M68Z512 M68Z512W SUPERVISOR M40Z300 M40Z300 M40Z300W THS Pin(1) VSS VOUT VSS
Note: 1. Connection of Threshold Select Pin (Pin 13) of SUPERVISOR (M40Z300/300W).
5/22
M48Z512A, M48Z512AY, M48Z512AV
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 3. Absolute Maximum Ratings
Symbol TA TSTG TBIAS TSLD(1) V IO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Temperature Under Bias Lead Solder Temperature for 10 seconds Input or Output Voltages M48Z512A/512AY Supply Voltage M48Z512AV Output Current Power Dissipation -0.3 to 4.6 20 1 V mA W Value 0 to 70 -40 to 85 -40 to 70 260 -0.3 to 7 -0.3 to 7.0 Unit C C C C V V
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
6/22
M48Z512A, M48Z512AY, M48Z512AV
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter Supply Voltage (V CC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M48Z512A/512AY 4.75 to 5.5V or 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 M48Z512AV 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns V V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 7. AC Measurement Load Circuit
DEVICE UNDER TEST
650
CL = 100pF or 30 pF
1.75V
CL includes JIG capacitance
AI03903
Note: Excluding open drain output pins; 50pF for M48Z512AV.
Table 5. Capacitance
Symbol C IN CIO(3) Parameter (1,2) Input Capacitance Input / Output Capacitance Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V (M48Z512A/Y) or 3.3V (M48Z512AV); sampled only, not 100% tested. 2. Outputs deselected. 3. At 25C.
7/22
M48Z512A, M48Z512AY, M48Z512AV
Table 6. DC Characteristics
M48Z512A/Y Sym Parameter Test Condition
(1)
M48Z512AV -85 Min Max 1 1 50 4 3 -0.3 2.2 0.6 VCC + 0.3 0.4 2.2 A A mA mA mA V V V V Unit
-70 / -85 Min Max 1 1 115 10 5 -0.3 2.2 0.8 V CC + 0.3 0.4 2.4
ILI(2) ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH
Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
0V VIN VCC 0V VOUT VCC E = VIL Outputs open E = VIH E VCC - 0.2V
IOL = 2.1mA IOH = -1mA
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. Outputs deselected.
OPERATING MODES The M48Z512A/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the switchover voltage (VSO), the control cirTable 7. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VCC 4.75 to 5.5V or 4.5 to 5.5V or 3.0 to 3.6V VSO to VPFD (min)(1) VSO(1) E VIH VIL VIL VIL X X
cuitry connects the battery which maintains data until valid power returns. The ZEROPOWER (R) RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
G X X VIL VIH X X
W X VIL VIH VIH X X
DQ0-DQ7 High Z D IN DOUT High Z High Z High Z
Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Swit chover Voltage. 1. See Table 11, page 14 for details.
8/22
M48Z512A, M48Z512AY, M48Z512AV
READ Mode The M48Z512A/Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripplethrough access of data from eight of 4,194,304 locations in the static storage array. Thus, the unique address specified by the 19 Address Inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and
G access times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 8. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01221
VALID tAXQX tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
Figure 9. Address Controlled, READ Mode AC Waveforms
A0-A18 tAVAV tAVQV DQ0-DQ7 DATA VALID
AI01220
tAXQX
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
9/22
M48Z512A, M48Z512AY, M48Z512AV
Table 8. READ Mode AC Characteristics
M48Z512A/Y Symbol Parameter
(1)
M48Z512A/Y/V -85 Min 85 Max ns 85 85 45 5 5 ns ns ns ns ns 35 25 5 ns ns ns Unit
-70 / -85 Min Max
tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX
READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
70 70 70 35 5 5 30 20 5
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. CL = 5pF.
10/22
M48Z512A, M48Z512AY, M48Z512AV
WRITE Mode The M48Z512A/Y/V is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from E or tWHAX from W prior to the initiation
of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 10. WRITE Enable Controlled, WRITE AC Waveforms
tAVAV A0-A18 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01222
tWHAX
tWHQX
Note: Output Enable (G) = High.
Figure 11. Chip Enable Controlled, WRITE AC Waveforms
tAVAV A0-A18 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01223
tELEH
tEHAX
Note: Output Enable (G) = High.
11/22
M48Z512A, M48Z512AY, M48Z512AV
Table 9. WRITE Mode AC Characteristics
M48Z512A/Y Symbol Parameter
(1)
M48Z512A/Y/V -85 Min 85 0 0 65 75 5 15 35 35 0 10 Max ns ns ns ns ns ns ns ns ns ns ns 30 75 75 5 ns ns ns ns Unit
-70 / -85 Min Max
tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2,3) tAVWH t AVEH tWHQX(2,3)
WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition
70 0 0 55 55 5 15 30 30 0 10 25 65 65 5
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
12/22
M48Z512A, M48Z512AY, M48Z512AV
Data Retention Mode With valid VCC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. Figure 12. Power Down/Up Mode AC Waveforms
The internal coin cell will maintain data in the M48Z512A/Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO , the battery is disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on Battery Storage Life refer to the Application Note AN1012.
VCC VPFD (max) VPFD (min) VSO VSS
tF tFB
tDR tRB DON'T CARE
tR tREC
RECOGNIZED
INPUTS
(Including E)
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
AI02385
Table 10. Power Down/Up AC Characteristics
Symbol tF(2) tFB(3) tR tRB tWPT tER Parameter (1) VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to V SS VCC Fall Time VPFD (min) to V PFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time M48Z512A/Y Write Protect Time M48Z512AV E Recovery Time 40 40 250 120 M48Z512A/Y M48Z512AV Min 300 10 150 10 1 40 150 Max Unit s s s s s ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
13/22
M48Z512A, M48Z512AY, M48Z512AV
Table 11. Power Down/Up Trip Points DC Characteristics
Symbol Parameter (1,2) M48Z512A VPFD Power-fail Deselect Voltage M48Z512AY M48Z512AV VSO tDR(3) M48Z512A/Y Battery Back-up Switchover Voltage M48Z512AV Expected Data Retention Time 10 2.5 V YEARS Min 4.5 4.2 2.8 Typ 4.6 4.3 2.9 3.0 Max 4.75 4.5 3.0 Unit V V V V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 3. At 25C.
Power Supply Decoupling and Undershoot Protection ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (see Figure 13) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount).
Figure 13. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
14/22
M48Z512A, M48Z512AY, M48Z512AV
PART NUMBERING Table 12. Ordering Information Scheme
Example: M48Z 512AY -70 PM 1
Device Type M48Z
Supply Voltage and Write Protect Voltage 512A = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 512AY = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V 512AV = V CC = 3.0 to 3.6V; V PFD = 2.8 to 3.0V
Speed -70 = 70ns (for M48Z512A/Y) -85 = 85ns (for M48Z512A/Y/V)
Package (1) PM = PMDIP32
Temperature Range 1 = 0 to 70C 9 = Extended Temperature (2)
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPH AT(R)) which is ordered separately under the part number "M4Zxx-BR00SH" in plastic tube or "M4Zxx-BR00SHTR" in Tape & Reel form. 2. Contact Sales Offices for availability of Extended Temperature. Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH" in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 13. SNAPHAT Battery Table
Part Number M4Z28-BR00SH M4Z32-BR00SH Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT Package SH SH
15/22
M48Z512A, M48Z512AY, M48Z512AV
PACKAGE MECHANICAL INFORMATION Figure 14. PMDIP32 - 32-pin Plastic DIP Module, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Note: Drawing is not to scale.
Table 14. PMDIP32 - 32-pin Plastic DIP Module, Package Mechanical Data
mm Symb Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 inches
16/22
M48Z512A, M48Z512AY, M48Z512AV
Figure 15. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Drawing is not to scale.
Table 15. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inch
17/22
M48Z512A, M48Z512AY, M48Z512AV
Figure 16. SH - 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note: Drawing is not to scale.
Table 16. SH - 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
18/22
M48Z512A, M48Z512AY, M48Z512AV
Figure 17. SH - 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note: Drawing is not to scale.
Table 17. SH - 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090 inches
19/22
M48Z512A, M48Z512AY, M48Z512AV
Figure 18. TSOP II 32 - 32-lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline
D
16
1
E1
E
17
32
b
e
A
A2 C A1 CP L
TSOP-d
Note: Drawing is not to scale.
Table 18. TSOP II 32 - 32-lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data
mm Symb Typ A A1 A2 b C D e E E1 L CP 1.27 0.05 0.95 0.30 0.12 20.82 - 11.56 10.03 0.40 0 Min Max 1.20 0.15 1.05 0.52 0.21 21.08 - 11.96 10.29 0.60 5 0.10 0.050 0.002 0.037 0.012 0.005 0.820 - 0.455 0.395 0.016 0 Typ Min Max 0.047 0.006 0.041 0.020 0.008 0.830 - 0.471 0.405 0.024 5 0.004 inches
20/22
M48Z512A, M48Z512AY, M48Z512AV
REVISION HISTORY Table 19. Revision History
Date March 2000 07/19/00 01/15/01 12/19/01 First Issue M48Z12AV added Changed LPSRAM device (Table 2) Reformatted; added temperature information (Table 5, 6, 8, 9, 10, 11); remove chipset option from Ordering Information (Table 12); remove reference to "clock" Revision Details
21/22
M48Z512A, M48Z512AY, M48Z512AV
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Swit zerland - United Kingdom - U.S.A. www.st.com
22/22

▲Up To Search▲

Price & Availability of M48Z512A-70PM1NBSP

	To Download M48Z512A-70PM1NBSP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .